IDF 08 Pt. 2

Hello happy reader,

Well, after that nondescript lunch thang, a turkey sammy, cardboard–tainted sweet and pasta salad, I headed over to meet w/the PCI folks. I sat down with Al Yanes, president and chair of the 918 member PCI-SIG, who met w/me to discuss v3 of PCIe, the Peripheral Component Interconnect Express bus. Here’s what I came away with…

The spec is on track for delivery in the second half of 2009. PCIe 3 requires full backward compatibility with earlier versions, including the same or a better power budget than PCIe 2. Performance–wise, they’re looking at 8 GTransfers/second as I mentioned last time, with an ultimate increase to 10 GT/s. Lower latencies, Data Reuse Hints, Atomic Operations and other optimizations will be part of the performance and functionality improvements. Data Reuse Hints, or DRH, addresses the mismatch between I/O data rates and latencies relative to throughput and latencies observed inside a CPU core or memory subsystem. DRH provide “explicit cache management hints (to) significantly reduce I/O to memory bandwidth utilization, system interconnect bandwidth, and associated power consumption,” according to the folks at Intel. The device driver identifies patterns in the bus I/O, usually copies of data already transacted, and attempts to substitute shorter versions. My guess would be that entropy encoding is used…

Atomic operations refer to processor–to–processor operations, which improve memory utilization. Their patents say Atomic Operations “…arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data.” I think the PCI folks borrowed that technique from InfiniBand, a bus used for short haul, low latency, high rate communication method in HPC or High Performance Computing applications.

To achieve the next level of data rates, PCIe 3 will use a new channel coding scheme. The existing 8b/10b encoding is being replaced with scrambling–only (no control characters) 128/130 encoding, a new one for me. This yields enough improvement in coding efficiency to kick it up to 10GT/s. BTW, scrambling is a technique whereby a known polynomial is applied to a data stream in a feedback topology. Because it’s deterministic, you can recover the original data by running the process in reverse.

Lastly, the PCI-SIG is working on an I/O Virtualization or IOV suite, a collection of specs that provide enable the direct sharing of PCI devices by a hypervisor, a supervisor application sandwiched between a host and any virtual OSs running on it…

OK, enough already with the PCI schtick! A veritable plethora of Atom–based netbooks and handheld multi–players were on hand to fondle. The players are PSP–sized, totally overloaded with features, and absurdly expensive. Examples include Yukyung Tech’s viliv, at (gulp) US$700 to $800, and Wibrain’s B1 series. At least the B1 runs Linux as well as Windows..That’s all for now. ’Till next time, continue to geek.

One Response to “IDF 08 Pt. 2”

  1. […] in August, I wrote a bit about Intel’s IDF here at Moscone. There’s plenty of coverage out there about the then […]