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MemCon 08 Pt. 1

My notes from Denali Software’s MemCon08, 07-24-08

We all are familiar with dynamic RAM on computer motherboards but most of this conference was concerned with NAND–based flash memory products. NAND storage is widespread in the form of “flash drives,” those little products that have completely replaced small capacity, highly portable sneakernet stuff, along with CompactFlash and other standards for removable consumer storage. What follows are my take–aways for this show…

Session 1: Dean Klein, Micron

Installed capacity for NAND flash in personal computers has, in one year’s time, reached what it took DRAM to achieve in a 6 year time frame. Significantly, from 1990 to 2008, the core voltage has dropped significantly, and it’s unlikely that core voltage will drop below 1 volt. Despite the prediction that 48 nm was thought to be the limit of fab technology, current technology provides a 34 nm architecture and that is likely to shrink further to 16 nm by 2020. DDR3 will move to 1.35 volts, further reducing power requirements and easing the expectation of ever higher performance through faster signaling.

DPD: DPD or Deep Power Down provides selective refresh rather than refreshing the whole memory array.

e–MMC: As with other subsystems in computers, memory manufacturers are looking to abstract NAND memory in order to mitigate the shortcomings of the technology, primarily wear level management. Even though flash memory has, by definition, no moving parts, a major shortcoming of NAND technology is “wear.” If a memory cell is used repeatedly, it will “wear out,” exhibiting increasingly higher error rates. So, smarter designers employ some level of read/write distribution of individual cells to minimize the wear and improve global device reliability. Abstraction places dedicated intelligence in between the memory elements themselves and the external controller to provide sophisticated wear leveling algorithms, along with an idealized and standardized external interface.

More to follow in Part 2…


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