IDF2009 Pt. II

Hello again happy reader,

This is your afternoon installment from IDF09. Specifically, the keynote from Sean Maloney and friends. The topic: Intel Architecture Innovates And Integrates

Intel’s first microprocessor or “computer on a chip,” the 4004, supported about 40 instruction while current generation microprocessors support over 700. Integration is a big part of their story, so how did they get to the current 32nm fabrication process?

Extending Nehalem Architecture

Itanium heads toward Tukwila versus Xeon heading toward Nehalem-EX microarchitecture. Nehalem-EX is designed for blade, rack and HPC (high performance computing) designs, up to 8 cores scalable up to 8 sockets, with over 20 new bullet–proofing or RAS features going into the Xeon line. Many of these RAS features are specifically aimed at virtualized environments, where one 8 socket server, with 8 cores in each socket, can run thousands of virtual machines simultaneously. If the server crashes, a major train wreck ensues…

The Powerpoint had a quote from Mark Seager of Lawrence Livermore, something to the effect of “…a SMP super–node on a chip.” SMP means Symmetrical MultiProcessing means many equally capable computers, allconnected to the same memory subsystems and working on the same problem. Taking Seager’s quote in context, what he’s saying is that the next generation Nehalem microarchitecture is what would be considered a “desktop supercomputer” a decade ago except now, it’s on a chip.


Intel’s upcoming Westmere-EP is designed for higher performance & efficiency, better security w/AES acceleration and Trusted Execution Technology. All that means more transactions on both client and server, with higher security.

Intel Mode Manager

Andy Bechtolsheim, co-founder of Sun Microsystems with Bill Joy, was brought on stage to talk about new, efficient micro–server products; complete, high performance servers in a form factor the size of a typical DVD case.

Maloney also mentioned their Jasper Forest architecture for high performance embedded and storage applications. Jasper Forest is a future family of low power Xeon embedded processors for communications and storage applications.


Core i5 and i7: Win7 optimization for performance, power and operational management, security. Management in particular was highlighted, with vPro’s ability to remote manage a computer, even without a functional browser. So, ISPs can manage their clueless customer’s machines remotely.


Programmable rendering feature: they showed a demo of a realtime ray tracing. Ray tracing is not usually real time! More on Larrabee tomorrow me thinks…


A nexgen desktop architecture, with AES acceleration, on–chip graphics, enhanced hyper=threading and “Turbo” dynamic resource management

The Future

Integrating yet more instructions into the big processors…

On to Bob Baker’s talk,  

Is Moore’s Law ending?

It’s a trade–off; either you increase the number of transistors or, reduce the cost. Baker discussed materials and process engineering and the need to invest in fundamental research.He then dug into specific on their process technologies and capabilities required to pull off 22 and 15nm fab…intersting but very tweaky stuff so, not in this blog I don’t!

All for today. Thanks for visiting and, until next, geek on!

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